Integrated circuits form the basis for many electronic systems. An integrated circuit typically includes a large number of transistors and other active and passive circuit elements that are formed on a single semiconductor die or chip and are interconnected to implement a desired function. The complexity of these integrated circuits requires the use of an ever increasing number of linked transistors and other circuit elements. For instance, ultra-large scale integration (ULSI) integrated circuits may have more than a million logic gates on a single chip.
Provisions must be made to electrically connect a die to the printed circuit board with which it is used and also to protect the die from damage or other external conditions that could hinder its operation. Package engineering, or packaging, is the field within semiconductor engineering that addresses these needs. Integrated circuits are generally mounted on printed circuit boards in “packages,” i.e., structures that provide an electrical interface with a printed circuit board and also protect a bare die and its electrical interconnects from damage, including damage due to moisture, vibration, and impact. A packaged die is generally attached to a metal leadframe or a substrate, electrically connected to the leadframe or substrate, and encapsulated with a ceramic enclosure or plastic “mold compound” for protection.
Occasionally, conventional packaging solutions may not afford adequate space savings on a printed circuit board. Especially in the case of memory devices, the functionality of multiple dies may be required while space for only one packaged die is available on a board. In such cases, using a “multi-chip module” (MCM), or single package containing multiple dies, is often considered. In some MCM's, dies are arranged side-by-side on a single substrate. However, depending on the application, this approach may not provide significant space savings over simply packaging multiple dies separately, a more common assembly process. Accordingly, it may be desired to stack multiple dies within a single package.
There are several benefits to stacked die packages. More functionality within a given area of board space may be achieved, since more silicon functions per area of board space (and per unit volume of application space) are possible. Eliminating individual packages for each die can contribute to significant size and weight reductions of printed circuit boards and electronic devices in which they are installed. Including two or more dies in one package decreases the number of components mounted on an application board, potentially reducing overall system cost. In addition, providing a single package for package assembly, electrical testing and handling may reduce manufacturing costs.
There have been numerous techniques developed for interconnecting a number of dies in a stack to form a system module. For instance, in U.S. Appl. Serial No. 2004/0113222, one or more vertical interconnect vias are formed in the individual integrated circuit dies to allow the subsequent interconnect of the die when they are stacked. The vias are filled with tungsten to form the interconnects. In other cases the vias are filled with copper.
While there are numerous advantages to a stacked die configuration, there are also associated problems. Specifically, larger and larger stacks create cooling problems. Because the chip stacks contain multiple dies, they generate more heat per unit volume, requiring greater heat dissipation, while at the same time providing significantly smaller surface areas which may be used as a heat sink. While vias filled with copper can ameliorate this problem to some extent by dissipating the heat to the surface of the die, the thermal conductivity of copper is nevertheless in many cases not sufficiently high to eliminate the problem of cooling. Another problem that arises when copper is employed is the relatively long time that is required to grow the bulk copper. For example, if a copper electroplating process is employed, it may take upwards of an hour to fill a via that is several hundred microns is depth.